1. Field of the Invention
The present invention relates to a test device for testing a combinatorial logic circuit, comprising a generator circuit for generating test bit sequences to N inputs of the combinatorial circuit in parallel, these test bit sequences comprising applying to each particular one of the N inputs at least two mutually opposed signal inversions between zero and one, each inversion being combined with an (N-1) bit word to the other inputs for ensuring transmission of the inversion to an output of the logic circuit, said test device furthermore comprising an output circuit for analyzing an output signal of the combinatorial circuit.
2. Prior Art
Such a device has important applications, principally in the testing of integrated logic circuits in CMOS technology. This technology allows a high degree of integration, and this requires tests on the correct functioning of the circuit not only at the end of manufacture but also when the device is mounted on an assembly such as a printed circuit board. For such an assembly, testing intervals are provided to alternate with the normal functioning.
A method as set forth in the Field of the Invention has been described in the research report RR533 issued in May 1985 and published by IMAG, 46 Avenue Felix Viallet 38031 Grenoble CEDEX FRANCE. This method avoids such faulty responses of the logic circuit in that certain malfunctions could make it behave like a sequential circuit as opposed to a combinatorial one.